Server/External PCIE Connectivity Worksteam: Difference between revisions
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===Documents=== | ===Documents=== | ||
https:// | https://drive.google.com/drive/folders/0AJSSbhm5kNnuUk9PVA | ||
===Past External PCIE Connectivity Events=== | ===Past External PCIE Connectivity Events=== | ||
Revision as of 20:06, 9 January 2023
Welcome to the OCP External PCIE Connectivity WIKI
External PCIE Connectivity is a Worksteam within the Server Project.
Leadership
Public Mailing List
- Page: https://ocp-all.groups.io/g/ocp-external-pcie-connectivity/
- Post: ocp-external-pcie-connectivity@OCP-All.groups.io
- Subscribe: ocp-external-pcie-connectivity+subscribe@OCP-All.groups.io
- Unsubscribe: ocp-external-pcie-connectivity+unsubscribe@OCP-All.groups.io
Scope
To document the various industry usage-model scenarios and requirements for rack-level disaggregated NVMe and/or CXL inter-connected Compute, Acceleration, Memory and Storage modules using PCIe Gen5 & Gen6 external Direct Attached(DAC), Active Electrical(AEC) and Active Optical(AOC) Cables. The Workstream will not explore any specific implementation solutions at this time; however, a future industry standards committee will be formed by willing members aiming to materialize the requirement output of this Workstream into a complete standard cabling specification.
Documents
https://drive.google.com/drive/folders/0AJSSbhm5kNnuUk9PVA