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! Name !! Format !! Version !! Submit Date !! Contributor !! Link !! Notes | ! Name !! Format !! Version !! Submit Date !! Contributor !! Link !! Notes | ||
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| FLW | | FLW CAD file 1.02 (Errata update) || STP || 1.02 || 1/4/2023 || Corey Hartman || [https://drive.google.com/file/d/12SaVz9NPKjkzKmu3v0KJ2_wfZ2a66Cu8/view?usp=share_link Link] || Errata update added missing rounds to PCB corners of CAD file, no change to spec. | ||
|- | |- | ||
| Errata || M-XIO Specification || RC4 || 12/12/2022 || Javier Lasa || TBD, will add link in Jan 2023 || Update SFF-TA-1016 pinouts, clarification of the usage of 3P3 AUX_MGMT. | | Errata || M-XIO Specification || RC4 || 12/12/2022 || Javier Lasa || TBD, will add link in Jan 2023 || Update SFF-TA-1016 pinouts, clarification of the usage of 3P3 AUX_MGMT. | ||
Revision as of 03:31, 7 January 2023
Welcome
Welcome to the OCP DC-MHS Sub-Project.
DC-MHS R1 envisions interoperability between key elements of datacenter, edge and enterprise infrastructure by providing consistent interfaces and form factors among modular building blocks.
DC-MHS R1 standardizes a collection of HPM (Host Processor Modules) form-factors and supporting ingredients to allow interoperability of HPMs and platforms.
There are six workstreams that comprise DC-MHS. The objectives of the six workstreams are the following:
- M-FLW (FulL Width HPM)
- Specify the requirements of a Full Width Host Processor Module (HPM). This is for use within products designed for minimum 19" rack, also known as compliant with EIA-310-E but can also accommodate larger 21" racks. This form factor enables a full width HPM usage for CPUs, DIMMs, and related features.
- M-DNO (DeNsity Optimized HPM)
- Outline the requirements of a family of partial width, DeNsity Optimized Host Processor Module (HPM) form factors within the OCP Modular 240 hardware system group of specifications (M-DNO for short). This M-DNO specification embodies design considerations for CPU, DIMMs, and other server processor related features commonly used by the industry today but is not limited to only those functions.
- M-XIO/PESTI (eXtended I/O Connectivity/PEripheral SideBand Tunneling Interface) :
- Outline the Modular Extensible I/O (M-XIO) source connector hardware strategy. An M-XIO source connector enables entry and exit points between sources such as Motherboards, Host Processor Modules & RAID Controllers, and peripheral subsystems such as PCIe risers, backplanes, etc. M-XIO includes the connector, high speed and management signal interface details and supported pinouts. Additionally, the workstream defines Interface (M-PESTI) base requirements for electrical and protocol compatibility between components of a DC-MHS platform. The M-PESTI protocol overloads a common PRSNT# signal with additional capabilities beyond simple presence/absence of a peripheral.
- M-PIC (Platform Infrastructure Connectivity)
- Defines and standardizes common elements needed to interface a Host Processor Module (HPM) to the platform/chassis infrastructure elements/subsystems within the DC-MHS 1.0 family of OCP servers. Standardization of the common interfaces and connectors enables hardware compatibility between DC-MHS HPMs and various DC-MHS system components.
- M-CRPS (Common Redundant Power Supply)
- Defines all the requirements for an M-CRPS internal redundant power supply used in Open Compute Project that could be used in different environments like home/office, datacenter, and high-performance computing, hence harmonizing the server power supply requirements used in the industry with the purpose of creating a standard specification that the customers and vendors of Enterprise and Hyperscale can use for their products.
- M-SIF (Shared InFrastructure)
- Improve interoperability related to shared infrastructure enclosures with multiple, serviceable modules. Modules containing elements (HPMs, DC-SCM, peripherals, etc.) are blind-matable and hot-pluggable into a shared infrastructure enclosure.
Disclaimer: Please do not submit any confidential information to the Project Community. All presentation materials, proposals, meeting minutes and/or supporting documents are published by OCP and are open to the public in accordance with OCP's Bylaws and IP Policy. This can be found on the OCP Policies page. If you have any questions please contact OCP.
Project Leadership
Sub-Project Leads
- Brian Aspnes (Intel)
- Shawn Dube (Dell)
Workstream Leads
- M-FLW: Brian Aspnes (Intel) and Corey Hartman (Dell)
- M-DNO: Dirk Blevins (Intel) and Mike Gregoire (Dell)
- M-XIO/PESTI: Charlie Ziegler (Dell) and Javier Lasa (Intel)
- M-PIC: Tim Lambert (Dell) and Cliff DuBay (Intel)
- M-CRPS: Aurelio Rodriguez Echevarria (Intel) and Jon Lewis (Dell)
- M-SIF: Dirk Blevins (Intel) and Greg Sellman (AMD)
Incubation Committee Representative
- Siamak Tavallaei (Google)
DC-MHS Wiki Administrator
- John Dinsmoor (Intel)
Current Status
DC-MHS R1 v1.0 specs have been approved by the OCP Incubation Committee in November 2022.
DC-MHS workstreams are working the DC-MHS R1 v1.1 specifications.
Note: M-SIF is a workstream new to DC-MHS. M-SIF is working on v1.0 specification.
Latest DC-MHS Specifications
| Type | Description | Version | Submit Date | Contributor | License | Notes |
|---|---|---|---|---|---|---|
| Specification | DC-MHS v1.0 specifications: M-FLW_R1_v1p0 M-DNO_R1_v1p0 M-XIO_R1_v1p0 M-PIC_R1_v1p0 M-CRPS_R1_v1p0 M-PESTI_R1_v1p0 |
R1-v1.0_RC | 9/28/2022 | DC-MHS CLA group | OWF | Reviewed in Oct meeting. Approved by the IC on 11/4/2022 All specifications can be found in the Contribution Database |
Working Documents, ECNs, and Errata
This sectin includes CAD, PDF Drawings, and other Collaterals from the DC-MHS Workstreams
| Name | Format | Version | Submit Date | Contributor | Link | Notes |
|---|---|---|---|---|---|---|
| FLW CAD file 1.02 (Errata update) | STP | 1.02 | 1/4/2023 | Corey Hartman | Link | Errata update added missing rounds to PCB corners of CAD file, no change to spec. |
| Errata | M-XIO Specification | RC4 | 12/12/2022 | Javier Lasa | TBD, will add link in Jan 2023 | Update SFF-TA-1016 pinouts, clarification of the usage of 3P3 AUX_MGMT. |
| FLW Rev 1.0 PDF Drawings | 1.01 | 10/12/2022 | Corey Hartman | Link | Link to FLW Drawings | |
| FLW Rev 1.0 CAD | STP | 1.01 | 9/23/2022 | Corey Hartman | Link | Link to the FLW CAD files |
| DNO Rev 1.0 CAD | STP | 1.01 | ||||
| DNO Rev 1.0 PDF Drawings | 1.0 |
Inactive Documents
This section includes Workstream specification errata and any other working documents.
| Type | Description | Version | Submit Date | Contributor | License | Notes |
|---|---|---|---|---|---|---|
Get Involved
Communication
- Project communication is done through https://ocp-all.groups.io/g/OCP-DC-MHS
- Post: OCP-DC-MHS@OCP-All.groups.io
- Subscribe: OCP-DC-MHS+subscribe@OCP-All.groups.io
- Unsubscribe: OCP-DC-MHS+unsubscribe@OCP-All.groups.io
- Please make sure to follow the steps until you receive 1) confirmation email from noreply@Groups.io 2) welcome email from OCP-DC-MHS@OCP-All.groups.io
- Please check your junk box and unblock noreply@Groups.io if you have trouble receiving the confirmation email
- To access the mailing list archives go to https://ocp-all.groups.io/g/OCP-DC-MHS
Meeting Schedule
For monthly public meetings:
- Schedule is TBD
- Each workstream has its own weekly meeting for companies that have signed the DC-MHS R1 CLA.
Recordings from Past Monthly Meeting Calls
- TBD
Slides from April 2022 OCP Tech Talks
| Presenters (Company) | Title | Video | Slides |
|---|---|---|---|
| Shawn Dube (Dell), Brian Aspnes (Intel) | DC-MHS Rev 1.0: Introduction and Overview (Datacenter - Modular Hardware System) | Video | Slides |
| Corey Hartman (Dell), Brian Aspnes (Intel) | DC-MHS: FulL Width HPMs (M-FLW) | Video | Slides |
| Mike Gregoire (Dell), Dirk Blevins (Intel) | DC-MHS: DeNsity Optimized HPMs (M-DNO) | Video | Slides |
| Cliff DuBay (Intel), Tim Lambert (Dell) | DC-MHS: Peripheral Infrastructure Connectivity (M-PIC) | Video | Slides |
| Charlie Ziegler (Dell), Javier Lasa (Intel) | DC-MHS: eXtensible I/O (M-XIO) | Video | Slides |
| Tim Lambert (Dell), Javier Lasa (Intel) | DC-MHS: PEripheral Sideband Tunneling Interface (M-PESTI) | Video | Slides |
| Aurelio Rodriguez (Intel), Jon Lewis (Dell) | DC-MHS: Common Redundant Power Supply (M-CRPS) | Video | Slides |
Slides/Recordings from October 2022 OCP Global Summit
| Presenter | Title | Video | Slides |
|---|---|---|---|
| Aurelio Rodriguez Echevarria (Intel) | Corey Hartman (Dell) | Tim Lambert (Dell) | Eduardo Estrada (Intel) | PANEL: DC-MHS R1 report-out and timeline | Video | Slides |
| Brian Aspnes (Intel) | Shawn Dube (Dell) | Jean-Marie Verdun (HPE) | Dharmesh Jani (Meta) | PANEL: Datacenter Modular Hardware System (DC-MHS) | Video | Slides |
| Todd Westhauser (Meta) | Vincent Nguyen (HPE) | Practical Usage of DC-MHS M-DNO Concepts | Video | Slides |
| Dirk Blevins (Intel) | Multi-host Modular Systems | Video | Slides |
OCP Marketplace Entries
The most recent documents will always be in the OCP Marketplace, Specifications & Design Collateral
or the OCP Marketplace, Orderable Products
Entries below are for ease of use and historical reference. Please use the marketplace links for the most recent documents.
| Type | Description | Version | Submit Date | Contributor | License | Notes |
|---|---|---|---|---|---|---|