Server/External PCIE Connectivity Worksteam: Difference between revisions
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===Scope=== | ===Scope=== | ||
To document the various industry usage-model scenarios and requirements for rack-level disaggregated NVMe and/or CXL inter-connected Compute, Acceleration, Memory and Storage modules using PCIe Gen5 & Gen6 external Direct Attached(DAC), Active Electrical(AEC) and Active Optical(AOC) Cables. The Workstream will not explore any specific implementation solutions at this time; however, a future industry standards committee will be formed by willing members aiming to materialize the requirement output of this Workstream into a complete standard cabling specification. | |||
===Documents=== | ===Documents=== | ||
Revision as of 16:52, 29 November 2022
Welcome to the OCP M-FLW WIKI
External PCIE Connectivity is a Worksteam within the Server Project.
Leadership
Scope
To document the various industry usage-model scenarios and requirements for rack-level disaggregated NVMe and/or CXL inter-connected Compute, Acceleration, Memory and Storage modules using PCIe Gen5 & Gen6 external Direct Attached(DAC), Active Electrical(AEC) and Active Optical(AOC) Cables. The Workstream will not explore any specific implementation solutions at this time; however, a future industry standards committee will be formed by willing members aiming to materialize the requirement output of this Workstream into a complete standard cabling specification.
Documents
- Coming Soon
Past External PCIE Connectivity Events
- Coming Soon