Editing Server/External PCIE Connectivity Worksteam

Revision as of 16:39, 29 November 2022 by Mohamad.elbatal (talk | contribs) (→‎Scope: To document the various industry usage model scenarios and requirements of rack-level disaggregated NVMe and/or CXL inter-connected Compute, Acceleration, Memory and Storage components with external PCIe Gen5 & Gen6 DAC, AEC & AOC cables)

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